Continued from part 4.
|Analog 1/3 (pdf)||Analog 2/3 (pdf)||Analog 3/3 (pdf)|
|Amplifier & ADC||Microcontroller||Power & Timing|
Part 1 contains the key elements: The differential amplifier and the ADC. This circuit needs to service each of the RadEye sensors, and it is therefore needed eight times. Following the reference design, the OPA2353 was used. Adjustable gain and adjustable offset are provided via digital potentiometers (AD5162). The ADC is continuously clocked, and it is set to accept a symmetrical +/- 2V input. Its outputs are buffered with a 74ACT541, because ribbon cables connect this part of the circuit with the memory boards.
Part 2 shows the microcontroller component. One 18F4520 each controls a set of four analog sections. These microcontrollers are primarily responsible for the digital potentiometers and for controlling the sensor input lines (scan, bin, ndr and most importantly, start). They communicate with the master controller via I2C.
Part 3 shows the remainder of the circuit. Mainly, this is the power conditioning section (analog power is separated from digital power through a choke), generation of the 3.8V reference, and the clock generator that was used in early development stages. In the final design, the crystal oscillator and the 74F74 divider are no longer used as those signals are provided from the main memory board.
|Figure 11: Schematic diagram of the timing generator. All signals are derived from the same 16MHz clock source, and a binary counter generates a 4MHz and a 2MHz signal. These signals are fed into an address decoder (74ALS139), which provides four negative 250μs pulses per clock cycle. Two of these are used for address increment and for memory write enable, respectively. A shift register delays the line signal by 6 clock cycles to synchronize it with the 6-cycle delay of the ADC.|
A shift register (74ALS164) is used to delay the module's /LINE signal by 6 clock cycles. The delayed line signal, /DLINE, is low whenever the ADC offers valid pixel data. /DLINE enables a 2-bit address decoder, which creates 4 sequential pulses during each clock cycle, each 250μs long (h/t Hartmut Langanke). The fourth pulse occurs 250μs after the rising edge of the clock signal and thus gives ample time for the buffered data lines to stabilize. This signal is called /MEMWR, and it is used to write data into memory. 250μs after /MEMWR goes high and stops the writing process, the rising edge of the second decoded line increments the address counters (provided that they are enabled via CLKEN). Figure 11 shows the first of the 5 address counter stages (lower part of the 74ALS393). Via ACLR, the address counters can be reset to zero. Moreover, when /DLINE is high, CLKEN can be pulsed to increment the counter address from the microcontroller.
To be continued...